It has been shown that strained Si has higher n and p carrier mobilities than unstrained Si. Increased carrier mobilities lead to higher performance in CMOS circuits such as microprocessors. One way to create strained-Si is to grow a thin single crystal Si layer on a relaxed single crystal substrate that has a higher in-plane lattice parameter than that of the Si. One such relaxed substrate is Si—Ge.
For embedded memory applications, it is desirable to create patterned SOI regions. High performance CMOS integrated circuits are made on the SOI regions, whereas the dynamic memory (DRAM) circuits are made on the bulk-Si regions. Details of forming patterned SOI regions are described by Davari et al. in U.S. Pat. No. 6,333,532.
In the semiconductor industry, there has recently been a high-level of activity using strained Si-based heterostructures to achieve high mobility structures for CMOS applications. Traditionally, the prior art method to implement this has been to grow strained Si layers on thick (on the order of from about 1 to about 5 micrometers) relaxed SiGe buffer layers.
Despite the high channel electron mobilities reported for prior art heterostructures; the use of thick SiGe buffer layers has several noticeable disadvantages associated therewith. First, thick SiGe buffer layers are not typically easy to integrate with existing Si-based CMOS technology. Second, the defect densities, including threading dislocations and misfit dislocations, are from about 105 to about 108 defects/cm2 which are still too high for realistic VSLI (very large scale integration) applications. Thirdly, the nature of the prior art structure precludes selective growth of the SiGe buffer layer so that circuits employing devices with strained Si, unstrained Si and SiGe materials are difficult, and in some instances, nearly impossible to integrate.
In order to produce relaxed SiGe material on a Si substrate, prior art methods typically grow a uniform, graded or stepped, SiGe layer to beyond the metastable critical thickness (i.e., the thickness beyond which dislocations form to relieve stress) and allow misfit dislocations to form, with the associated threading dislocations (TDs), through the SiGe buffer layer. Various buffer structures have been used to try to modulate the formation of misfit dislocations in the structures and thereby to decrease the TD density.
Another prior art approach, such as described in U.S. Pat. Nos. 5,461,243 and 5,759,898, both to Ek, et al., provides a structure with a strained and defect free semiconductor layer wherein a new strain relieve mechanism operates so that the SiGe buffer layer relaxes without the generation of TDs within the SiGe layer.
Neither the conventional approaches, nor the alternative approaches described in the Ek, et al. patents provide a solution that substantially satisfies the material demands for device applications, i.e., sufficiently low TD density, substantially little or no misfit dislocation density and control over where the TD defects will be formed. As such, there is a continued need for developing a new and improved method of forming relaxed SiGe-on-insulator substrate materials which are thermodynamically stable against defect production.